From Bihar to SEMICON India: How Shweta Suman is building Swadeza for the world

Swadeza began with a simple question. What would "Made in India" really look like if globally relevant technology were built from places people rarely associate with deeptech?

That question became a company. Today, Swadeza is being built from Bihar with ambitions that go well beyond its geography. It also reflects a larger shift in India's technology landscape, about where the country's next generation of technology companies can come from, and who gets to build them.

A journey in the opposite direction

Founder Shweta Suman's path has been anything but linear. She went to school in Oman, studied engineering at BIT Mesra, returned to Oman, and eventually moved back to Bihar after marriage. Rather than look elsewhere for opportunity, she chose to build here.

That choice matters in the context of the state. Bihar is often discussed in terms of migration, with talent and opportunity leaving. Suman's journey runs the other way: coming back, building a technology company, entering India's startup ecosystem, and eventually seeing Swadeza on one of the country's most visible semiconductor stages.

One company, three businesses

Swadeza operates across semiconductor technology, IT consulting and development, and 360° digital marketing. Its deeptech work is increasingly focused on AI-native semiconductor engineering.

On the software side, it builds platforms for government and public-sector teams. The company describes itself as women-led, and says its engineers average 11 years of experience across fabless semiconductors, consumer platforms and government deployments.

It also built an automated AI verification system for government recruitment for the Government of Bihar, which it says cut turnaround from several months to weeks.

The problem FORGE is targeting

Before a chip goes to fabrication, engineers must prove the design behaves exactly as specified. That verification work is among the most time-consuming stages of chip development, and errors caught after tape-out are expensive.

Swadeza's argument is that general-purpose AI assistants struggle at this scale. As a design grows, the assistant's prompt fills with unrelated and conflicting fragments, and answer quality drops. Its semiconductor platform, FORGE, instead keeps the chip in a cited map, sends a language model only what a given question touches, and converts what it learns into deterministic models, so each run is meant to finish faster and cost less than the last.

Four products across the chip lifecycle

FORGE is designed to bring AI-native workflows across the chip lifecycle, from verification and physical design to post-silicon validation and standard cells.

DV-FORGE handles verification. It reads a chip's reference manual into a map and generates the verification plan, coverage model and UVM testbench from it. The company says DV-FORGE has been used on OpenTitan-class SoCs, signing off OpenTitan Earlgrey, a taped-out root-of-trust chip, in 30 days, and finding seven bugs across roughly 40 IP blocks and 2,581 registers. Its derivative, Darjeeling, was signed off in 21 days, with most of that time spent in regression. Swadeza also claims 80% fewer tokens than an AI assistant, and says it has run the pipeline on reference manuals from NXP, STMicroelectronics, Renesas and Infineon.

PD-FORGE is being developed for physical-design closure, tracing signoff violations back to the stage that caused them. It links reports from every stage, run and tool to the same nets, across 26 Synopsys, Cadence, Siemens and open-source back-ends, and is in closed testing ahead of a Q4 2026 production release.

PS-FORGE, for post-silicon validation and debug, and SC-FORGE, which aims to produce provably optimal standard cells, are both still in development.

FORGE is deployed on-premises. In an industry where chip designs are among a company's most sensitive IP, keeping data inside customer environments removes a major barrier to adopting AI tools.

Swadeza says it is building with professors from BIT Patna and with Signitude, a fabless semiconductor company.

Bihar on the semiconductor stage

At SEMICON India 2026, Swadeza showcased its semiconductor technology alongside some of the industry's most recognised names. The event was also FORGE's first public demonstration, at startup pod 6.

The fifth edition of SEMICON India ran from 17 to 19 September under the theme "Silicon to Systems: Building the Ecosystem". It came two months after the Cabinet approved Semicon 2.0, a ₹1,27,500 crore second phase of India's chip mission.

Swadeza was subsequently included in Forbes India's photo coverage of the event, in the same visual showcase as IBM and Tata Electronics.

For a company that chose to build from Bihar, that moment carried significance far beyond publicity. It placed a Bihar-built product in the same frame as global semiconductor leaders.

A state trying to enter the chip economy

Bihar is making its own push into the sector. The state cabinet approved its Semiconductor Policy 2026 earlier this year, seeking fabrication units, display fabs and chip design facilities, and a Bihar Semiconductor Mission has been set up to oversee implementation.

Most of that policy targets manufacturing investment. Swadeza represents a different kind of participation: design tooling built locally and aimed at chip teams anywhere.

Building from India, for the world

Swadeza's broader vision is to build from India for a global market. The near-term tests are clear: moving PD-FORGE into production, and turning conversations from SEMICON into on-premises deployments with paying chip teams.

If it gets there, Swadeza will be a proof point that India's deeptech companies do not need to start in the usual hubs, and that the next wave of builders may come from places the ecosystem has overlooked.